BURST=SOFTWARE, EDGE=RISING, PDN=POWERDOWN, CLKS=11_CLOCKS_10_BITS, START=NO_START
A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur.
| SEL | Selects which of the ADC[7:0] pins are to be sampled and converted. Bit 0 selects Pin ADC0, bit 1 selects pin AD1,…, and bit 7 selects pin ADC7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All zeroes is equivalent to 0x01. |
| CLKDIV | The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. |
| BURST | Burst mode 0 (SOFTWARE): Conversions are software controlled and require 11 clocks. 1 (BURST): The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that is in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start. |
| CLKS | This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits). 0 (11_CLOCKS_10_BITS): 11 clocks / 10 bits 1 (10_CLOCKS_9_BITS): 10 clocks / 9 bits 2 (9_CLOCKS_8_BITS): 9 clocks / 8 bits 3 (8_CLOCKS_7_BITS): 8 clocks / 7 bits 4 (7_CLOCKS_6_BITS): 7 clocks / 6 bits 5 (6_CLOCKS_5_BITS): 6 clocks / 5 bits 6 (5_CLOCKS_4_BITS): 5 clocks / 4 bits 7 (4_CLOCKS_3_BITS): 4 clocks / 3 bits |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |
| PDN | Power mode 0 (POWERDOWN): The A/D converter is in Power-down mode. 1 (RUNNING): The A/D converter is operational. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |
| START | When the BURST bit is 0, these bits control whether and when an A/D conversion is started (also see Figure 56): 0 (NO_START): No start (this value should be used when clearing PDN to 0). 1 (START_CONVERSION_NOW): Start conversion now. 2 (CTOUT_15): Start conversion when the edge selected by bit 27 occurs on CTOUT_15 (combined timer output 15). 3 (CTOUT_8): Start conversion when the edge selected by bit 27 occurs on CTOUT_8 (combined timer output 8). 4 (ADCTRIG0): Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 input. 5 (ADCTRIG1): Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 input. 6 (MCOA2): Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2. 7 (RESERVED_): Reserved. |
| EDGE | This bit is significant only when the START field contains 0x2 -0x6. In these cases: 0 (RISING): Start conversion on a rising edge on the selected signal. 1 (FALLING): Start conversion on a falling edge on the selected signal. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |